2-20
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Table 2-10. Embedded SRAM in LatticeECP Family
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block Performance of LatticeECP Family
For further inf ormation on the sysDSP bloc k, please see details of additional technical information at the end of this
data sheet.
Device DSP Block 9x9 Multiplier 18x18 Multiplier 36x36 Multiplier
LFECP6 4 32 16 4
LFECP10 5 40 20 5
LFECP15 6 48 24 6
LFECP20 7 56 28 7
LFECP33 8 64 32 8
LFECP40 10 80 40 10
Device EBR SRAM Block
Total EBR SRAM
(Kbits)
LFECP6 10 92
LFECP10 30 276
LFECP15 38 350
LFECP20 46 424
LFECP33 58 535
LFECP40 70 645
Device DSP Block
DSP Performance
MMAC
LFECP6 4 3680
LFECP10 5 4600
LFECP15 6 5520
LFECP20 7 6440
LFECP33 8 7360
LFECP40 10 9200
