2-14
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Figure 2-16. Memory Core Reset
For further infor mation on sysMEM EBR block, please see the details of additional technical documentation at the
end of this data sheet.
sysDSP Block
The LatticeECP-DSP f amily provides a sysDSP bloc k making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) filters; Fast Four ier Transfor ms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased b y
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-17 compares the serial and the
parallel implementations.
Q
SET
D
L
CLR
Output Data
Latches
Memory Core
Port A[17:0]
Q
SET
D
Port B[17:0]
RSTB
GSRN
Programmable Disable
RSTA
L
CLR
