2-11
Architecture
Lattice Semiconductor LatticeECP/EC Family Data Sheet
Table 2-5. PLL Signal Descriptions
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or r unt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates
the DCS Block Macro.
Figure 2-13. DCS Block Primitive
Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Signal I/O Description
CLKI I Clock input from external pin or routing
CLKFB I PLL feedback input from CLKOP, clocknet, or external pin
RST I “1” to reset PLL
CLKOS O PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP O PLL output clock to clock tree (No phase shift)
CLKOK O PLL output to clock tree through secondary clock divider
LOCK O “1” indicates PLL LOCK to CLKI
DDAMODE I Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
DDAIZR I Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
DDAILAG I Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
DDAIDEL[2:0] I Dynamic Delay Input
DDAOZR O Dynamic Delay Zero Output
DDAOLAG O Dynamic Delay Lag/Lead Output
DDAODEL[2:0] O Dynamic Delay Output
DCS
CLK0
DCSOUT
CLK1
SEL
