4-10
Pinout Information
Lattice Semiconductor MachXO Family Data Sheet
82 PT9A 1 PT12C 1 T
83 GND - GND -
84 PT8B 1 C PT11B 1 C
85 PT8A 1 T PT11A 1 T
86 PT7D 1 PCLK1_1**** PT10B 1 PCLK1_1****
87 PT6F 0 PCLK1_0**** PT9B 1 PCLK1_0****
88 PT6D 0 C PT8F 0 C
89 PT6C 0 T PT8E 0 T
90 VCCAUX - VCCAUX -
91 VCC - VCC -
92 PT5B 0 PT6D 0
93 PT4B 0 PT6F 0
94 VCCIO0 0 VCCIO0 0
95 PT3D 0 C PT4B 0 C
96 PT3C 0 T PT4A 0 T
97 PT3B 0 PT3B 0
98 PT2B 0 C PT2B 0 C
99 PT2A 0 T PT2A 0 T
100**
GNDIO0
GNDIO7
-
GNDIO0
GNDIO7
-
*Supports true LVDS outputs.
**Double bonded to the pin.
***NC for "E" devices.
****Primary clock inputs are single-ended.
LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP (Cont.)
Pin
Number
LCMXO1200 LCMXO2280
Ball
Function Bank
Dual
Function Differential
Ball
Function Bank
Dual
Function Differential
