• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • LCMXO1200LUTSE-3T100IES PDF文件及第48页内容在线浏览

LCMXO1200LUTSE-3T100IES

LCMXO1200LUTSE-3T100IES首页预览图
型号: LCMXO1200LUTSE-3T100IES
PDF文件:
  • LCMXO1200LUTSE-3T100IES PDF文件
  • LCMXO1200LUTSE-3T100IES PDF在线浏览
功能描述: MachXO Family Data Sheet
PDF文件大小: 942.59 Kbytes
PDF页数: 共95页
制造商: LATTICE[Lattice Semiconductor]
制造商LOGO: LATTICE[Lattice Semiconductor] LOGO
制造商网址: http://www.latticesemi.com
捡单宝LCMXO1200LUTSE-3T100IES
PDF页面索引
120%
4-4
Pinout Information
Lattice Semiconductor MachXO Family Data Sheet
Power Supply and NC (Cont.)
Signal 132 csBGA
1
256 ftBGA
1
324 ftBGA
1
VCC H3, P6, G12, C7 G7, G10, K7, K10 F14, G11, G9, H7, L7, M9
VCCIO0 LCMXO640: B11, C5
LCMXO1200/2280: C5
LCMXO640: F8, F7, F9, F10
LCMXO1200/2280: F8, F7
G8, G7
VCCIO1 LCMXO640: L12, E12
LCMXO1200/2280: B11
LCMXO640: H11, G11, K11, J11
LCMXO1200/2280: F9, F10
G12, G10
VCCIO2 LCMXO640: N2, M10
LCMXO1200/2280: E12
LCMXO640: L9, L10, L8, L7
LCMXO1200/2280: H11, G11
J12, H12
VCCIO3 LCMXO640: D2, K3
LCMXO1200/2280: L12
LCMXO640: K6, J6, H6, G6
LCMXO1200/2280: K11, J11
L12, K12
VCCIO4 LCMXO640: None
LCMXO1200/2280: M10
LCMXO640: None
LCMXO1200/2280: L9, L10
M12, M11
VCCIO5 LCMXO640: None
LCMXO1200/2280: N2
LCMXO640: None
LCMXO1200/2280: L8, L7
M8, R9
VCCIO6 LCMXO640: None
LCMXO1200/2280: K3
LCMXO640: None
LCMXO1200/2280: K6, J6
M7, K7
VCCIO7 LCMXO640: None
LCMXO1200/2280: D2
LCMXO640: None
LCMXO1200/2280: H6, G6
H6, J7
VCCAUX P7, A7 T9, A8 M10, F9
GND
2
F1, P9, J14, C9, A10, B4, L13,
D13, P2, N11, E1, L2
A1, A16, F11, G8, G9, H7, H8, H9,
H10, J7, J8, J9, J10, K8, K9, L6,
T1, T16
E14, F16, H10, H11, H8, H9, J10,
J11, J4, J8, J9, K10, K11, K17, K8,
K9, L10, L11, L8, L9, N2, P14, P5,
R7
NC
3
LCMXO640: E4, E5, F5, F6, C3,
C2, G4, G5, H4, H5, K5, K4, M5,
M4, P2, P3, N5, N6, M7, M8, N10,
N11, R15, R16, P15, P16, M11,
L11, N12, N13, M13, M12, K12,
J12, F12, F13, E12, E13, D13,
D14, B15, A15, C14, B14, E11,
E10, E7, E6, D4, D3, B3, B2
LCMXO1200: None
LCMXO2280: None
1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of
GND logic connections from the die to the common package GND plane.
3. NC pins should not be connected to any active signals, VCC or GND.
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价