4-3
Pinout Information
Lattice Semiconductor MachXO Family Data Sheet
Power Supply and NC
Signal 100 TQFP
1
144 TQFP
1
100 csBGA
2
VCC LCMXO256/640: 35, 90
LCMXO1200/2280: 17, 35, 66, 91
21, 52, 93, 129 P7, B6
VCCIO0 LCMXO256: 60, 74, 92
LCMXO640: 80, 92
LCMXO1200/2280: 94
LCMXO640: 117, 135
LCMXO1200/2280: 135
LCMXO256: H14, A14, B5
LCMXO640: B12, B5
VCCIO1 LCMXO256: 10, 24, 41
LCMXO640: 60, 74
LCMXO1200/2280: 80
LCMXO640: 82, 98
LCMXO1200/2280: 117
LCMXO256: G1, P1, P10
LCMXO640: H14, A14
VCCIO2 LCMXO256: None
LCMXO640: 29, 41
LCMXO1200/2280: 70
LCMXO640: 38, 63
LCMXO1200/2280: 98
LCMXO256: None
LCMXO640: P4, P10
VCCIO3 LCMXO256: None
LCMXO640: 10, 24
LCMXO1200/2280: 56
LCMXO640: 10, 26
LCMXO1200/2280: 82
LCMXO256: None
LCMXO640: G1, P1
VCCIO4 LCMXO256/640: None
LCMXO1200/2280: 44
LCMXO640: None
LCMXO1200/2280: 63
—
VCCIO5 LCMXO256/640: None
LCMXO1200/2280: 27
LCMXO640: None
LCMXO1200/2280: 38
—
VCCIO6 LCMXO256/640: None
LCMXO1200/2280: 20
LCMXO640: None
LCMXO1200/2280: 26
—
VCCIO7 LCMXO256/640: None
LCMXO1200/2280: 6
LCMXO640: None
LCMXO1200/2280: 10
—
VCCAUX LCMXO256/640: 88
LCMXO1200/2280: 36, 90
53, 128 B7
GND
3
LCMXO256: 40, 84, 62, 75, 93, 12,
25, 42
LCMXO640: 40, 84, 81, 93, 62, 75,
30, 42, 12, 25
LCMXO1200/2280: 9, 41, 59, 83,
100, 76, 50, 26
16, 59, 88, 123, 118, 136, 83, 99,
37, 64, 11, 27
LCMXO256: N9, B9, G14, B13,
A4, H1, N2, N10
LCMXO640: N9, B9, A10, A4,
G14, B13, N3, N10, H1, N2
NC
4
—
1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
2. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
3. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of
GND logic connections from the die to the common package GND plane.
4. NC pins should not be connected to any active signals, VCC or GND.
