4-2
Pinout Information
Lattice Semiconductor MachXO Family Data Sheet
Pin Information Summary
Pin Type
LCMXO256C/E LCMXO640C/E
100 TQFP 100 csBGA 100 TQFP 144 TQFP 100 csBGA 132 csBGA 256 ftBGA
Single Ended User I/O 78 78 74 113 74 101 159
Differential Pair User I/O
1
38 38 17 43 17 42 79
Muxed 6666666
TAP 4444444
Dedicated (Total Without Supplies) 5555555
VCC 2224244
VCCAUX 1112122
VCCIO
Bank0 3322224
Bank1 3322224
Bank2 — — 22224
Bank3 — — 22224
GND 8 8 10 12 10 12 18
NC 00000052
Single Ended/Differential I/O
per Bank
Bank0 41/20 41/20 18/5 29/10 18/5 26/11 42/21
Bank1 37/18 37/18 21/4 30/11 21/4 27/12 40/20
Bank2 — — 14/2 24/9 14/2 21/9 36/18
Bank3 — — 21/6 30/13 21/6 27/10 40/20
1. These devices support emulated LVDS outputs. LVDS inputs are not supported.
Pin Type
LCMXO1200C/E LCMXO2280C/E
100 TQFP 144 TQFP 132 csBGA 256 ftBGA 100 TQFP 144 TQFP 132 csBGA 256 ftBGA 324 ftBGA
Single Ended User I/O 73 113 101 211 73 113 101 211 271
Differential Pair User I/O
1
27 48 42 105 30 47 41 105 134
Muxed 666666666
TAP 444444444
Dedicated (Total Without Supplies) 555555555
VCC 444424446
VCCAUX 222222222
VCCIO
Bank0 111211122
Bank1 111211122
Bank2 111211122
Bank3 111211122
Bank4 111211122
Bank5 111211122
Bank6 111211122
Bank7 111211122
GND 8 12 12 18 8 12 12 18 24
NC 000000000
Single Ended/Differential I/O
per Bank
Bank0 10/3 14/6 13/5 26/13 9/3 13/6 12/5 24/12 34/17
Bank1 8/2 15/7 13/5 28/14 9/3 16/7 14/5 30/15 36/18
Bank2 10/4 15/7 13/6 26/13 10/4 15/7 13/6 26/13 34/17
Bank3 11/5 15/7 14/7 28/14 11/5 15/7 14/7 28/14 34/17
Bank4 8/3 14/5 13/5 27/13 8/3 14/4 13/4 29/14 35/17
Bank5 5/2 10/4 8/2 22/11 5/2 10/4 8/2 20/10 30/15
Bank6 10/3 15/6 13/6 28/14 10/4 15/6 13/6 28/14 34/17
Bank7 11/5 15/6 14/6 26/13 11/5 15/6 14/6 26/13 34/17
1. These devices support on-chip LVDS buffers for left and right I/O Banks.
