3-18
DC and Switching Characteristics
Lattice Semiconductor MachXO Family Data Sheet
Switching Test Conditions
Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Figure 3-5.
Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition R
1
C
L
Timing Ref. V
T
LVTTL and LVCMOS settings (L -> H, H -> L)
∞
0pF
LVTTL, LVCMOS 3.3 = 1.5V —
LVCMOS 2.5 = V
CCIO
/2 —
LVCMOS 1.8 = V
CCIO
/2 —
LVCMOS 1.5 = V
CCIO
/2 —
LVCMOS 1.2 = V
CCIO
/2 —
LVTTL and LVCMOS 3.3 (Z -> H)
188 0pF
1.5
V
OL
LVTTL and LVCMOS 3.3 (Z -> L) V
OH
Other LVCMOS (Z -> H) V
CCIO
/2 V
OL
Other LVCMOS (Z -> L) V
CCIO
/2 V
OH
LVTTL + LVCMOS (H -> Z) V
OH
- 0.15 V
OL
LVTTL + LVCMOS (L -> Z) V
OL
- 0.15 V
OH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
V
T
R1
CL
Test Point
