3-16
DC and Switching Characteristics
Lattice Semiconductor MachXO Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
MachXO “C” Sleep Mode Timing
Parameter Descriptions Conditions Min. Max. Units
f
IN
Input Clock Frequency (CLKI, CLKFB) 25 420 MHz
f
OUT
Output Clock Frequency (CLKOP, CLKOS) 25 420 MHz
f
OUT2
K-Divider Output Frequency (CLKOK) 0.195 210 MHz
f
VCO
PLL VCO Frequency 420 840 MHz
f
PFD
Phase Detector Input Frequency 25 — MHz
AC Characteristics
t
DT
Output Clock Duty Cycle Default duty cycle selected
3
45 55 %
t
PH
4
Output Phase Accuracy — 0.05 UI
t
OPJIT
1
Output Clock Period Jitter
Fout ≥ 100MHz — +/-120 ps
Fout < 100MHz — 0.02 UIPP
t
SK
Input Clock to Output Clock Skew Divider ratio = integer — +/-200 ps
t
W
Output Clock Pulse Width At 90% or 10%
3
1—ns
t
LOCK
2
PLL Lock-in Time — 150 µs
t
PA
Programmable Delay Unit 100 450 ps
t
IPJIT
Input Clock Period Jitter — +/-200 ps
t
FBKDLY
External Feedback Delay — 10 ns
t
HI
Input Clock High Time 90% to 90% 0.5 — ns
t
LO
Input Clock Low Time 10% to 10% 0.5 — ns
t
RST
RST Pulse Width 10 — ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
2. Output clock is valid after t
LOCK
for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. CLKOS as compared to CLKOP output.
Rev. A 0.19
Symbol Parameter Device Min. Typ. Max Units
t
PWRDN
SLEEPN Low to Power Down All — — 400 ns
t
PWRUP
SLEEPN High to Power Up
LCMXO256 — — 400 µs
LCMXO640 — — 600 µs
LCMXO1200 — — 800 µs
LCMXO2280 — — 1000 µs
t
WSLEEPN
SLEEPN Pulse Width All 400 — — ns
t
WAWAKE
SLEEPN Pulse Rejection All — — 100 ns
Rev. A 0.19
SLEEPN
t
PWRUP
Power Down Mode
t
PWRDN
t
WSLEEPN
or t
WAWAKE
I/O
