3-13
DC and Switching Characteristics
Lattice Semiconductor MachXO Family Data Sheet
MachXO External Switching Characteristics
1
Over Recommended Operating Conditions
Parameter Description Device
-5 -4 -3
UnitsMin. Max. Min. Max. Min. Max.
General I/O Pin Parameters (Using Global Clock without PLL)
1
t
PD
Best Case t
PD
Through 1 LUT
LCMXO256 — 3.5 — 4.2 — 4.9 ns
LCMXO640 — 3.5 — 4.2 — 4.9 ns
LCMXO1200 — 3.6 — 4.4 — 5.1 ns
LCMXO2280 — 3.6 — 4.4 — 5.1 ns
t
CO
Best Case Clock to Output - From PFU
LCMXO256 — 4.0 — 4.8 — 5.6 ns
LCMXO640 — 4.0 — 4.8 — 5.7 ns
LCMXO1200 — 4.3 — 5.2 — 6.1 ns
LCMXO2280 — 4.3 — 5.2 — 6.1 ns
t
SU
Clock to Data Setup - To PFU
LCMXO256 1.3 — 1.6 — 1.8 — ns
LCMXO640 1.1 — 1.3 — 1.5 — ns
LCMXO1200 1.1 — 1.3 — 1.6 — ns
LCMXO2280 1.1 — 1.3 — 1.5 — ns
t
H
Clock to Data Hold - To PFU
LCMXO256 -0.3 — -0.3 — -0.3 — ns
LCMXO640 -0.1 — -0.1 — -0.1 — ns
LCMXO1200 0.0 — 0.0 — 0.0 — ns
LCMXO2280 -0.4 — -0.4 — -0.4 — ns
f
MAX_IO
Clock Frequency of I/O and PFU Register
LCMXO256 — 600 — 550 — 500 MHz
LCMXO640 — 600 — 550 — 500 MHz
LCMXO1200 — 600 — 550 — 500 MHz
LCMXO2280 — 600 — 550 — 500 MHz
t
SKEW_PRI
Global Clock Skew Across Device
LCMXO256 — 200 — 220 — 240 ps
LCMXO640 — 200 — 220 — 240 ps
LCMXO1200 — 220 — 240 — 260 ps
LCMXO2280 — 220 — 240 — 260 ps
1. General timing numbers based on LVCMOS2.5V, 12 mA.
Rev. A 0.19