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quency after a load transient as well as to mask PWM comparator output against noise and spikes.
The system has not an inter nal clock, b ecause this is a hys teretic control ler, so the turn on puls e will start if three
conditions are met contempor arily : the FB pin voltage i s low er than the refere nce voltage, the minimum o ff time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.
1.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage
(0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the P WM comparator output
goes high and sets the fl ip-flop outpu t, turning on the hig h side MOSF ET. Thi s condition i s latched to avoid noi se
spike. A fter the on-time ( cal culated as descr ibed in the previous section) the system resets the fl ip-flop and then
turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 1.
The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC
error. Fur ther the sys tem regulates the output voltage valley v alue not the aver age, as in the Fi gure 3 is show n.
So the voltage ripple on the output capaci tor is a source of DC static error (as the PCB traces) . To compensate
the DC errors, an integrator network must be intr oduced in the control lo op, by connectin g the output voltage to
the INT pin through a cap acitor and the FB pin to the INT pin directly as in Figure 4. Th e internal integrator am-
plifier with the exter nal capac itor C
INT 1
intr oduces a DC pole i n the control l oop. C
INT 1
also provides an AC path
for output ripple.
Figu re 3. Va lley regulatio n
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in or der to c ompensate the t otal s tatic er rors. A v oltage clamper wit hin the devi ce fo rces INT pi n v oltage
ranges from V
REF
-50mV, V
REF
+150mV. This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case of the ripple amplitude is large r than 150mV, a capacitor C
INT 2
can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherw ise the integrator can operate out of its linear ran ge. Choose
C
INT 1
according to the following equation:
Eq 5
where GINT =50 µs is the integrator transconductance,
α
OUT
is the output divider ratio given from Eq4 and F
U
is the cl ose loop bandwidth. This equation also holds if C
INT2
is connected between INT pin and ground. C
INT2
is given by:
Time
Vout
Vref
<Vout>
DC Error Offset
INT1
g
INT
α
OUT
⋅
2 π F
u
⋅⋅
--------------------------------- -=
