11/25
L6995
1.6 Protecti on and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of
the regulated val ue, P GOOD is high. If a hard over v oltage or an under voltage oc curs, the device is latched: low
side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects
an overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply
has to be removed, and restart with the correct sequence.
These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV
fault).
1.7 Drivers
The integr ated high-current dri vers allow using differ ent size of power MO SFET, maintaining fast s witching tran-
sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHAS E pin for return (floating
driver). The driver for the low side MOSFET uses the VD R pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the sam e time, avoidi ng a high current to flow from V IN to GN D. Wh en high side MOSFET
is tur ned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt-
age on P HASE pin r each es 250mV . When low side is turned off, high side remains off until LGA TE pin v oltage
reac hes 500mV. Thi s is important since the dr iver can w ork properly wi th a l arge range of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate char ge and the switchi ng frequency. S o the power di ssipati on of the devic e is functi on of the ex-
ternal power MOSFET gate charge and switching frequency.
Eq 14
The maximum gate charge values for the low side and high side are given from:
Eq 15
Eq 16
Where f
SW0
= 500Khz . The eq uations above are valid for T
J
= 150°C. If the system temperature is lower the Q
G
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is Q
MAXLS
= 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
2 APPL ICATION INFORMATION
2.1 20A Demo bo ard description
The demoboard sh ows the devi ce operation in general purpos e app lications. The evaluation board all ows using
only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device
through the J1. Output current in excess of 20A can be reached dependently on the MO SFET type. The S W1
is used to start the device (when the supplies are already present) and to select the PFM/PWM mode.
P
driver
V
cc
Q
gTOT
F
SW
⋅⋅=
Q
MAXHS
f
SW0
f
SW
------------ -
75nC⋅=
Q
MAXLS
f
SW0
f
SW
------------ -
125nC⋅=
