SCLS467B − FEBRUAR Y 2003 − REVISED MAY 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A
, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A
) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR
low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q
outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
A B Q Q
L X X L H
X HXL
†
H
†
X XLL
†
H
†
H L ↑
H ↓ H
↑ L H
†
These outputs are based on the
assumption that the indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
logic diagram, each multivibrator (positive logic)
CLR
C
ext
R
ext
/C
ext
R
B
A
Q
Q
