SCLS467B − FEBRUAR Y 2003 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Qualification in Accordance With
AEC-Q100
†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
D Typical V
OHV
(Output V
OH
Undershoot)
>2.3 V at V
CC
= 3.3 V, T
A
= 25°C
D Supports Mixed-Mode Voltage Operation on
All Ports
D Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
D Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
D I
off
Supports Partial-Power-Down Mode
Operation
D Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
D Overriding Clear Terminates Output Pulse
D Glitch-Free Power-Up Reset on Outputs
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V V
CC
operation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,
the A
input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A
input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C
ext
and R
ext
/C
ext
(positive) and an external resistor
connected between R
ext
/C
ext
and V
CC
. To obtain variable pulse durations, connect an external variable
resistance between R
ext
/C
ext
and V
CC
. The output pulse duration also can be reduced by taking CLR low.
ORDERING INFORMATION
T
A
PACKAGE
‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 105°C TSSOP − PW Tape and reel SN74LV123ATPWRQ1 L123ATQ
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1B
1CLR
1Q
2Q
2C
ext
2R
ext
/C
ext
GND
V
CC
1R
ext
/C
ext
1C
ext
1Q
2Q
2CLR
2B
2A
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