256/512/1K/2K/4K x 9 Asynchronous FIFO
CY7C419/21/25/29/33
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06001 Rev. *A Revised December 30, 2002
19/21/25/29/
Features
• Asynchronous first-in first-ou t (FIF O) buffe r me morie s
• 256 x 9 (CY7C419)
• 512 x 9 (CY7C421)
• 1K x 9 (CY7C425)
• 2K x 9 (CY7C429)
• 4K x 9 (CY7C433)
• Dual-ported RAM cell
• High-spe ed 50.0- MHz read/w rite inde pend ent of
depth/width
• Low operating power: I
CC
= 35 mA
• Empty and Full flags (Half Full flag in standalon e)
• TTL compatible
• Retransmit in standalone
• Expan dable in width
• PLCC, 7x7 TQFP, SOJ, 300-mil and 600-mil DIP
• Pin compatible and functionally equival ent to IDT7200,
IDT7201, IDT7202, IDT7203, IDT7204, AM7200, AM7201,
AM7202, AM7203, and AM7204
Functional Description
The CY7C419, CY7C420/1, CY7C424/5, CY7C428/9, and
CY7C432/3 are first-in first-out (FIFO) memories offered in
600-mil wide and 300-mil wide packages. They are, respec-
tively, 256, 512, 1 ,024, 2,048, and 4,096 w ords by 9-bit s wide.
Each FIFO memory is organized such that the data is read in
the same sequential order that it was written. Full and Empty
flags are pro vided to prevent ov errun and underrun. Three ad-
ditional pins are also prov ided to facilitat e unlimited exp ansion
in width, depth, o r both. The dept h expansion technique steers
the contro l signa ls from on e devic e to anoth er in paral lel, thu s
eliminating the serial addition of propagation delays, so that
throughp ut is not reduc ed. Data is s teered in a si milar manne r .
The read and write operations may be asynchronous; each
can occur at a rate of 50.0 MHz. The write operation occurs
when the write (W
) signa l is LO W . R ead occurs when read (R)
goes LOW. The nine data outputs go to the high-impedance
state when R
is HIGH.
A Half Full (H F
) output f lag is provided th at is valid in the sta n-
dalone and width expansion configurations. In the depth ex-
pansion configuration, this pin provides the expansion out
(XO
) informa tion that i s used to te ll the nex t FIFO th at it will be
activated.
In the sta nda lone a nd width expan sion c onfigu rati ons, a LO W
on the retransmit (RT
) input causes the FIFOs to retransmit
the data. Read enable (R
) and write enable (W) must both be
HIGH during retransmit, and then R is used to access the data.
The CY7C419, CY7C420, CY7C421, CY7C424, CY7C425,
CY7C4 28, CY7C429, CY 7C432, and C Y7C433 are fab ricated
using an advanced 0.65-micron P-well CMOS technology. In-
put ESD protec tio n is greater tha n 200 0V and latch-up is pre-
vented by careful layout and guard rings.
