8.0 USART (Continued)
rates may be created by using appropriate divisors. The 16x
clock is then divided by 16 to provide the rate for the serial
shift registers of the transmitter and receiver.
TABLE 4. Baud Rate Divisors
(1.8432 MHz Prescaler Output)
Baud Baud Rate
Rate Divisor − 1
(N-1)
110 (110.03) 1046
134.5
(134.58)
855
150 767
300 383
600 191
1200 95
1800 63
2400 47
3600 31
4800 23
7200 15
9600 11
19200 5
38400 2
Note: The entries in
Table 4
assume a prescaler output of 1.8432 MHz. In the
asynchronous mode the baud rate could be as high as 987.5k.
TABLE 5. Prescaler Factors
Prescaler Prescaler
Select Factor
00000 NO CLOCK
00001 1
00010 1.5
00011 2
Prescaler Prescaler
Select Factor
00100 2.5
00101 3
00110 3.5
00111 4
01000 4.5
01001 5
01010 5.5
01011 6
01100 6.5
01101 7
01110 7.5
01111 8
10000 8.5
10001 9
10010 9.5
10011 10
10100 10.5
10101 11
10110 11.5
10111 12
11000 12.5
11001 13
11010 13.5
11011 14
11100 14.5
11101 15
11110 15.5
11111 16
10131741
FIGURE 23. USART BAUD Clock Generation
10131742
FIGURE 24. USART BAUD Clock Divisor Registers
COP8SG Family
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