5.0 Functional Description (Continued)
The device comes out of reset with both the WATCH-
DOG logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
C
clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
C
–32 t
C
clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
5.9.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
tialization, the user must ensure that the RESET pin is held
low until the device is within the specified V
CC
voltage. An
R/C circuit on the RESET pin with a delay 5 times (5x)
greater than the power supply rise time or 15 µs whichever is
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in
Figure 9
.
5.9.2 On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON
register. When enabled, the device generates an internal
reset as V
CC
rises to a voltage level above 2.0V. The on-chip
reset circuitry is able to detect both fast and slow rise times
on V
CC
(V
CC
rise time between 10 ns and 50 ms).To guar-
antee an on-chip power-on-reset, V
CC
must start at a voltage
less than the start voltage specified in the DC characteris-
tics. Also, if V
CC
be lowered to the start voltage before
powering back up to the operating range. If this is not pos-
sible, it is recommended that external reset be used.
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly, or through a
pull-up resistor, to V
CC
. The output of the power-on reset
detector will always preset the Idle timer to 0FFF(4096 t
C
).
At this time, the internal reset will be generated.
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The
internal reset will perform the same functions as external
reset. The user is responsible for ensuring that V
CC
is at the
minimum level for the operating frequency within the 4096
t
C
. After the underflow, the logic is designed such that no
additional internal resets occur as long as V
CC
remains
above 2.0V.
The contents of data registers and RAM are unknown fol-
lowing the on-chip reset.
10131714
RC
>
5x power supply rise time or 15 µs, whichever is greater.
FIGURE 9. Reset Circuit Using External Reset
10131715
FIGURE 10. Reset Timing (Power-On Reset Enabled)
with V
CC
Tied to RESET
10131716
FIGURE 11. Reset Circuit Using Power-On Reset
COP8SG Family
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