1
Data sheet acquired from Harris Semiconductor
SCHS177
CD74HC297,
CD74HCT297
High-Speed CMOS Logic
Digital Phase-Locked-Loop
Features
• Digital Design Avoids Analog Compensation Errors
• Easily Cascadable for Higher Order Loops
• Useful Frequency Range
- K-Clock. . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (T yp)
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)
• Dynamically Variable Bandwidth
• Very Narrow Bandwidth Attainable
• Power-On Reset
• Output Capability
- Standard. . . . . . . . . . . . . . . . . . . . XORPD
OUT
, ECPD
OUT
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D
OUT
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• CD74HC297 Types
- Operation Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V
- High Noise ImmunityN
IL
= 30%, N
IH
= 30% of V
CC
at 5V
• CD74HCT297 Types
- Operation Voltage. . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V
- Direct LSTTL Input Logic Compatibility
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility I
I
≤ 1µA at V
OL
, V
OH
Description
The Harris CD74HC297 and CD74HCT297 are high-speed
silicon gate CMOS devices that are pin-compatible with low
power Schottky TTL (LSTTL).
These devices are designed to provide a simple, cost-eff ec-
tive solution to high-accuracy, digital, phase-locked-loop appli-
cations. They contain all the necessary circuits, with the
e xception of the divide-b y-N counter, to build first-order
phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided f or maximum flexibility. The
input signals for the EXCLUSIVE-OR phase detector must
hav e a 50% duty factor to obtain the maximum lock-range .
Proper partitioning of the loop function, with many of the build-
ing blocks external to the package, makes it easy for the
designer to incorporate ripple cancellation (see Figure 2) or to
cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally programmable
according to the K-counter function table. With A, B, C and D
all LOW, the K-counter is disabled. With A HIGH and B, C and
D LOW, the K-counter is only three stages long, which widens
the bandwidth or capture range and shortens the lock time of
the loop . When A, B, C and D are all programmed HIGH, the
K-counter becomes sev enteen stages long, which narrows
the bandwidth or capture range and lengthens the lock time.
Real-time control of loop bandwidth by manipulating the A to
D inputs can maximize the overall performance of the digital
phase-locked-loop.
The CD74HC297 and CD74HCT297 can perform the classic
first order phase-locked-loop function without using analog
components. The accuracy of the digital phase-locked-loop
(DPLL) is not affected by V
CC
and temperature variations but
depends solely on accuracies of the K-clock and loop propa-
gation dela ys .
Pinout
CD74HC297, CD74HCT297 (PDIP)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (
o
C) PACKAGE
PKG.
NO.
CD74HC297E -55 to 125 16 Ld PDIP E16.3
CD74HCT297E -55 to 125 16 Ld PDIP E16.3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B
A
EN
CTR
K
CP
I/D
CP
D/U
GND
I/D
OUT
V
CC
D
φA
2
ECPD
OUT
XORPD
OUT
φB
φA
1
C
November 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
File Number 1852.1
[ /Title
(CD74
HC297
,
CD74
HCT29
7)
Sub-
ect
(High-
Speed
CMOS
Logic
Digi-
tal
Phase-
Locked
