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CAT25128LI.G

CAT25128LI.G首页预览图
型号: CAT25128LI.G
PDF文件:
  • CAT25128LI.G PDF文件
  • CAT25128LI.G PDF在线浏览
功能描述: 128-Kb SPI Serial CMOS EEPROM
PDF文件大小: 216.78 Kbytes
PDF页数: 共20页
制造商: ONSEMI[ON Semiconductor]
制造商LOGO: ONSEMI[ON Semiconductor] LOGO
制造商网址: http://www.onsemi.com
捡单宝CAT25128LI.G
PDF页面索引
120%
CAT25128
http://onsemi.com
10
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP
is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP
going low will have no effect on any write
operation to the Status Register. The WP
pin function is
blocked when the WPEN bit is set to “0”. The WP
input
timing is shown in Figure 8.
Figure 7. WRSR Timing
0123 45678 10911121314
SCK
SI
MSB
HIGH IMPEDANCE
DATA IN
15
SO
7 6 5 4 3 2 10
0000000 1
OPCODE
Dashed Line = mode (1, 1)
CS
Figure 8. WP Timing
SCK
WP
Dashed Line = mode (1, 1)
WP
CS
t
WPH
t
WPS
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