www.awinic.com.cn 8 Copyright © 2016 SHANGHAI AWINIC TECHNOLOGY CO., LTD
I
2
C INTERFACE TIMING
Interface Clock frequency
(Repeat-start) Start condition hold time
(Repeat-start) Start condition setup time
Rising time of SDA and SCL
Falling time of SDA and SCL
Stop condition setup time
Time between start and stop condition
SDA
SCL
t
BUF
t
LOW
t
HD:STA
t
HD:DAT
t
R
t
HIGH
t
F
t
SU:DAT
t
SU:STA
t
SP
t
SU:STO
VIH
VIL
StopStop Start Start
VIH
VIL
Fig 4 I
2
C INTERFACE TIMING