®
AS7C3364PFD32B
AS7C3364PFD36B
1/31/05; v.1.1 Alliance Semiconductor P. 13 of 19
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
Din
Dout
t
CD
t
ADVH
t
LZOE
t
OE
t
LZC
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1
A2
A3
CE1
t
HZOE
DSEL Suspend
Read
Q(A1)
Read
Q(A1)
Suspend
Write
D(A
2
)
ADV
Burst
Read
Q(A
3Ý01
)
ADV
Burst
Read
Q(A
3Ý10
)
ADV
Burst
Read
Q(A
3Ý11
)
Read
Q(A2)
Read
Q(A3)
