AS7C3364PFD32B
AS7C3364PFD36B
®
1/31/05; v.1.1 Alliance Semiconductor P. 10 of 19
Snooze Mode Electrical Characteristics
Timing characteristics over operating range
Parameter Sym
–200 –166 –133
Unit Notes
1
1 See “Notes” on page 16.
Min Max Min Max Min Max
Clock frequency f
Max
–200
–166–133MHz
Cycle time t
CYC
5–
6–7.5–ns
Clock access time t
CD
–3.0
–3.5–4.0ns
Output enable LOW to data valid t
OE
–3.0
–3.5–4.0ns
Clock HIGH to output Low Z t
LZC
0–
0–0–ns2,3,4
Data output invalid from clock HIGH t
OH
1.5 –
1.5 – 1.5 – ns 2
Output enable LOW to output Low Z t
LZOE
0–
0–0–ns2,3,4
Output enable HIGH to output High Z t
HZOE
–3.0
– 3.5 – 4.0 ns 2,3,4
Clock HIGH to output High Z t
HZC
–3.0
– 3.5 – 4.0 ns 2,3,4
Output enable HIGH to invalid output t
OHOE
0–
0–0–ns
Clock HIGH pulse width t
CH
2.0 –
2.4 – 2.5 – ns 5
Clock LOW pulse width t
CL
2.3 –
2.4 – 2.5 – ns 5
Address setup to clock HIGH t
AS
1.4 –
1.5 – 1.5 – ns 6
Data setup to clock HIGH t
DS
1.4 –
1.5 – 1.5 – ns 6
Write setup to clock HIGH t
WS
1.4 –
1.5 – 1.5 – ns 6,7
Chip select setup to clock HIGH t
CSS
1.4 –
1.5 – 1.5 – ns 6,8
Address hold from clock HIGH t
AH
0.4 –
0.5 – 0.5 – ns 6
Data hold from clock HIGH t
DH
0.4 –
0.5 – 0.5 – ns 6
Write hold from clock HIGH t
WH
0.4 –
0.5 – 0.5 – ns 6,7
Chip select hold from clock HIGH t
CSH
0.4 –
0.5 – 0.5 – ns 6,8
ADV
setup to clock HIGH t
ADVS
1.4 –
1.5 – 1.5 – ns 6
ADSP
setup to clock HIGH t
ADSPS
1.4 –
1.5 – 1.5 – ns 6
ADSC
setup to clock HIGH t
ADSCS
1.4 –
1.5 – 1.5 – ns 6
ADV
hold from clock HIGH t
ADVH
0.4 –
0.5 – 0.5 – ns 6
ADSP
hold from clock HIGH t
ADSPH
0.4 –
0.5 – 0.5 – ns 6
ADSC
hold from clock HIGH t
ADSCH
0.4 –
0.5 – 0.5 – ns 6
Description Conditions Symbol Min Max Units
Current during Snooze Mode ZZ > V
IH
I
SB2
30 mA
ZZ active to input ignored t
PDS
2cycle
ZZ inactive to input sampled t
PUS
2cycle
ZZ active to SNOOZE current t
ZZI
2cycle
ZZ inactive to exit SNOOZE current t
RZZI
0
