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AS7C33512PFS32A-133TQI

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型号: AS7C33512PFS32A-133TQI
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功能描述: 3.3V 512K x 32/36 pipelined burst synchronous SRAM
PDF文件大小: 541.38 Kbytes
PDF页数: 共19页
制造商: ALSC[Alliance Semiconductor Corporation]
制造商LOGO: ALSC[Alliance Semiconductor Corporation] LOGO
制造商网址: http://www.alsc.com
捡单宝AS7C33512PFS32A-133TQI
PDF页面索引
120%
®
AS7C33512PFS32A
AS7C33512PFS36A
12/23/04, v 2.6 Alliance Semiconductor 6 of 19
Write enable truth table (per byte)
Key: X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
Asynchronous Truth Table
Notes:
1. X means “Don’t Care”
2. ZZ pin is pulled down internally
3. For write cycles that follows read cycles, the output buffers must be disabled with OE
, otherwise data bus contention will occur.
4. Snooze mode means power down state of which stand-by current does not depend on cycle times
5. Deselected means power down state of which stand-by current depends on cycle times
Burst sequence table
Function GWE BWE BWa BWb BWc BWd
Write All Bytes
LXXXXX
HLLLLL
Write Byte a
HLLHHH
Write Byte c and d
HLHHLL
Read
HHXXXX
HLHHHH
Operation ZZ OE I/O Status
Snooze mode H X High-Z
Read
L L Dout
L H High-Z
Write L X Din, High-Z
Deselected L X High-Z
Interleaved burst address (LBO = 1) Linear burst address (LBO = 0)
A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 A1 A0
Starting Address 0 0 0 1 1 0 1 1 Starting Address 0 0 0 1 1 0 1 1
First Increment 0 1 0 0 1 1 1 0 First Increment 0 1 1 0 1 1 0 0
Second Increment 1 0 1 1 0 0 0 1 Second Increment 1 0 1 1 0 0 0 1
Third Increment 1 1 1 0 0 1 0 0 Third Increment 1 1 1 0 0 1 1 0
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