ii
ii
i
PEMPEM
PEMPEM
PEM
2.4G2.4G
2.4G2.4G
2.4G
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDRb SDRAM-DDR
b SDRAM-DDR
AS4DDR32M72PBG
AS4DDR32M72PBG
Rev. 1.2 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Austin Semiconductor, Inc.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, but
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst. AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command. The device supports
concurrent auto precharge if the command to the other bank
does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. This “earliest valid
stage” is determined as if an explicit precharge command
was issued at the earliest possible time, without violating
tRAS (MIN).The user must not issue another command to the
same bank until the precharge time (tRP) is completed. This
is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, without violating tRAS
(MIN).
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ
bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE
command will be truncated. The open page which the READ
burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is
nonpersistent, so it must be issued each time a refresh is
required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each DDR SDRAM requires
AUTO REFRESH cycles at an average interval of 7.8125µs
(maximum).
To allow for improved efficiency in scheduling and switching
between tasks, some flexibility in the absolute refresh interval
is provided. A maximum of eight AUTO REFRESH commands
can be posted to any given DDR SDRAM, meaning that the
maximum absolute interval between any AUTO REFRESH
command and the next AUTO REFRESH command is 9 x
7.8125µs (70.3µs). This maximum absolute interval is to
allow future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, without
allowing excessive drift in tAC between updates.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during the
AUTO REFRESH period. The AUTO REFRESH period begins
when the AUTO REFRESH command is registered and ends
tRFC later.
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). The DLL is automatically
disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (200 clock cycles must
then occur before a READ command can be issued). Input
signals except CKE are “Don’t Care” during SELF REFRESH.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable prior to CKE going
back HIGH. Once CKE is HIGH, the DDR SDRAM must have
NOP commands issued for tXSNR, because time is required
for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
