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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated
4.3.25.2 Power, Reset, and Clock Management (PRCM)
NOTE
For more information, see PRCM section of the device TRM.
Table 4-27. PRCM Signal Descriptions
SIGNAL NAME DESCRIPTION TYPE BALL
clkout1 Device Clock output 1. Can be used externally for devices with non-
critical timing requirements, or for debug, or as a reference clock on
GPMC as described in Table 5-46 GPMC/NOR Flash Interface
Switching Characteristics - Synchronous Mode - Default and Table 5-
48 GPMC/NOR Flash Interface Switching Characteristics -
Synchronous Mode - Alternate.
O K23, L4
clkout2 Device Clock output 2. Can be used externally for devices with non-
critical timing requirements, or for debug.
O H5, J25
clkout3 Device Clock output 3. Can be used xternally for devices with non-
critical timing requirements, or for debug.
O H25
porz Power on Reset (active low). This pin must be asserted low until all
device supplies are valid (see reset sequence/requirements)
I F19
resetn Device Reset Input I K24
rstoutn Reset out (Active low). This pin asserts low in response to any global
reset condition on the device.
(2)
O E20
xi_osc0 System Oscillator OSC0 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
I Y12
xi_osc1 Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used
I AC11
xo_osc0 System Oscillator OSC0 Crystal output O AB12
xo_osc1 Auxiliary Oscillator OSC1 Crystal output O AA11
xref_clk0 External Reference Clock 0. For Audio and other Peripherals. I J25
xref_clk1 External Reference Clock 1. For Audio and other Peripherals. I J24
xref_clk2 External Reference Clock 2. For Audio and other Peripherals. I H24
xref_clk3 External Reference Clock 3. For Audio and other Peripherals. I H25
RMII_MHZ_50_CLK
(1)
RMII Reference Clock (50MHz). This pin is an input when external
reference is used or output when internal reference is used.
IO P5
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V
IH
and V
IL
must be less than V
HYS
.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.3.25.3 System Direct Memory Access (SDMA)
NOTE
For more information, see the DMA Controllers / System DMA section of the device TRM.
Table 4-28. SDMA Signal Descriptions
SIGNAL NAME DESCRIPTION TYPE BALL
dma_evt1 System DMA Event Input 1 I G1, L4
dma_evt2 System DMA Event Input 2 I H3, H5
dma_evt3 System DMA Event Input 3 I H2
