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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated
Table 4-7. GPMC Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION TYPE BALL
gpmc_a20 GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O A5, E7
(3)
, L4
gpmc_a21 GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O B6, D6
(3)
, H2
gpmc_a22 GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O A6, C5
(3)
, H6
gpmc_a23 GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O B5, H5, C10, G4
gpmc_a24 GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O D7
(3)
, D10, G3
gpmc_a25 GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O C6
(3)
, F6, E10
gpmc_a26 GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O A5
(3)
, M1, B10
gpmc_a27 GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
O B6
(3)
, D8, C7, E8
gpmc_cs0 GPMC Chip Select 0 (active low) O F3
gpmc_cs1 GPMC Chip Select 1 (active low) O A6
gpmc_cs2 GPMC Chip Select 2 (active low) O G4
gpmc_cs3 GPMC Chip Select 3 (active low) O G3
gpmc_cs4 GPMC Chip Select 4 (active low) O H2
gpmc_cs5 GPMC Chip Select 5 (active low) O H6
gpmc_cs6 GPMC Chip Select 6 (active low) O H5
gpmc_cs7 GPMC Chip Select 7 (active low) O L4
gpmc_clk
(1)(2)
GPMC Clock output IO L4
gpmc_advn_ale GPMC address valid active low or address latch enable O H5
gpmc_oen_ren GPMC output enable active low or read enable O G5
gpmc_wen GPMC write enable active low O G6
gpmc_ben0 GPMC lower-byte enable active low O H2
gpmc_ben1 GPMC upper-byte enable active low O H6
gpmc_wait0 GPMC external indication of wait 0 I F6
gpmc_wait1 GPMC external indication of wait 1 I H5, L4
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V
IH
and V
IL
must be less than V
HYS
.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See Table 5-46 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 5-48
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
(3) The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in
the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should
be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to
keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
4.3.7 Timers
NOTE
For more information, see the Timers section of the device TRM.
Table 4-8. Timers Signal Descriptions
SIGNAL NAME DESCRIPTION TYPE BALL
timer1 PWM output/event trigger input IO H21, H6
