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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated
Table 4-6. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION TYPE BALL
ddr1_d24 EMIF1 Data Bus IO T23
ddr1_d25 EMIF1 Data Bus IO T25
ddr1_d26 EMIF1 Data Bus IO T24
ddr1_d27 EMIF1 Data Bus IO P21
ddr1_d28 EMIF1 Data Bus IO N21
ddr1_d29 EMIF1 Data Bus IO P22
ddr1_d30 EMIF1 Data Bus IO P23
ddr1_d31 EMIF1 Data Bus IO P24
ddr1_dqm0 EMIF1 Data Mask O AE23
ddr1_dqm1 EMIF1 Data Mask O W22
ddr1_dqm2 EMIF1 Data Mask O U21
ddr1_dqm3 EMIF1 Data Mask O P25
ddr1_dqs0 Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO AD22
ddr1_dqsn0 Data strobe 0 invert IO AE22
ddr1_dqs1 Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO Y24
ddr1_dqsn1 Data strobe 1 invert IO Y25
ddr1_dqs2 Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO V24
ddr1_dqsn2 Data strobe 2 invert IO V25
ddr1_dqs3 Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO R24
ddr1_dqsn3 Data strobe 3 invert IO R25
ddr1_vref0 Reference Power Supply EMIF1 A Y20
4.3.6 GPMC
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
Table 4-7. GPMC Signal Descriptions
SIGNAL NAME DESCRIPTION TYPE BALL
gpmc_ad0 GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO F1
gpmc_ad1 GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO E2
gpmc_ad2 GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
IO E1
gpmc_ad3 GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
IO C1
gpmc_ad4 GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
IO D1
gpmc_ad5 GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
IO D2
gpmc_ad6 GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
IO B1
gpmc_ad7 GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
IO B2