Copyright © 2016–2017, Texas Instruments IncorporatedTerminal Configuration and Functions
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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
C7 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual
Voltage
LVCMOS
PU/PD
vin2b_clk1 2 I
vout2_clk No 4 O
emu7 5 O
eQEP1_index 10 IO 0
pr1_edio_data_in2 12 I 0
pr1_edio_data_out2 13 O
gpio3_30
gpmc_a27
gpmc_a18
14 IO
Driver off 15 I
E8 vin2a_hsync0 vin2a_hsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual
Voltage
LVCMOS
PU/PD
vin2b_hsync1 3 I
vout2_hsync No 4 O
emu8 5 O
uart9_rxd 7 I 1
spi4_sclk 8 IO 0
kbd_row2 9 I 0
eQEP1_strobe 10 IO 0
pr1_uart0_cts_n 11 I 1
pr1_edio_data_in3 12 I 0
pr1_edio_data_out3 13 O
gpio3_31
gpmc_a27
14 IO
Driver off 15 I
B8 vin2a_vsync0 vin2a_vsync0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual
Voltage
LVCMOS
PU/PD
vin2b_vsync1 3 I
vout2_vsync No 4 O
emu9 5 O
uart9_txd 7 O
spi4_d1 8 IO 0
kbd_row3 9 I 0
ehrpwm1A 10 O
pr1_uart0_rts_n 11 O
pr1_edio_data_in4 12 I 0
pr1_edio_data_out4 13 O
gpio4_0 14 IO
Driver off 15 I