Copyright © 2016–2017, Texas Instruments IncorporatedTerminal Configuration and Functions
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46
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
R2 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual
Voltage
LVCMOS
PU/PD
rmii0_rxd1 1 I 0
mii0_rxd1 3 I 0
vin2a_vsync0 4 I
vin1b_vsync1 5 I 0
spi4_d0 7 IO 0
uart4_ctsn 8 IO 1
pr1_mii0_rxd1 11 I 0
pr2_pru1_gpi9 12 I
pr2_pru1_gpo9 13 O
gpio5_24 14 IO
Driver off 15 I
P3 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual
Voltage
LVCMOS
PU/PD
rmii0_rxer 1 I 0
mii0_rxer 3 I 0
vin2a_hsync0 4 I
vin1b_hsync1 5 I 0
spi4_d1 7 IO 0
uart4_txd 8 O
pr1_mii0_rxer 11 I 0
pr2_pru1_gpi8 12 I
pr2_pru1_gpo8 13 O
gpio5_23 14 IO
Driver off 15 I
P4 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv9 Yes Dual
Voltage
LVCMOS
PU/PD
rmii0_crs 1 I 0
mii0_crs 3 I 0
vin2a_de0 4 I
vin1b_de1 5 I 0
spi4_sclk 7 IO 0
uart4_rxd 8 I 1
pr1_mii0_crs 11 I 0
pr2_pru1_gpi7 12 I
pr2_pru1_gpo7 13 O
gpio5_22 14 IO
Driver off 15 I