Dn
Processor
DQ and DM
IO Buffer
DDR
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_23
Processor
DQS
IO Buffer
DDR
DQS
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
DQSn-
DQSn+
SPRS906_PCB_DDR3_22
AS
=
Rtt
A1
A2
AT
VTT
SPRS906_PCB_DDR3_21
371
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Applications, Implementation, and LayoutCopyright © 2016–2017, Texas Instruments Incorporated
Figure 7-21. ADDR_CTRL Routing for One DDR3 Device
7.2.2.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 7-22
and Figure 7-23 show these topologies.
Figure 7-22. DQS Topology
Figure 7-23. DQ/DM Topology
