AS-
AS+
A1 A2
Processor
Differential Clock
Output Buffer
DDR Differential CK Input Buffers
Routed as Differential Pair
A3
AT
Rcp
Clock Parallel
Terminator
A1 A2
A3
AT
AS-
AS+
Rcp
Cac
DDR_1V5
0.1 µF
+
–
+
–
+
–
SPRS906_PCB_DDR3_12
AS
=
Rtt
A1
A2
A3
A4 AT
VTT
A3
SPRS906_PCB_DDR3_11
366
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Applications, Implementation, and Layout Copyright © 2016–2017, Texas Instruments Incorporated
Figure 7-11. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
7.2.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 7-12 shows the topology of the CK net classes and Figure 7-13 shows the topology for the
corresponding ADDR_CTRL net classes.
Figure 7-12. CK Topology for Two DDR3 Devices
