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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Applications, Implementation, and LayoutCopyright © 2016–2017, Texas Instruments Incorporated
7.2.2.9 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 7-8 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 7-8. Bulk Bypass Capacitors
NO. PARAMETER MIN MAX UNIT
1 vdds_ddrx bulk bypass capacitor count
(1)
1 Devices
2 vdds_ddrx bulk bypass total capacitance 22 μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
7.2.2.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 7-9 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 7-9.
Table 7-9. High-Speed Bypass Capacitors
NO. PARAMETER MIN TYP MAX UNIT
1 HS bypass capacitor package size
(1)
0201 0402 10 Mils
2 Distance, HS bypass capacitor to processor being bypassed
(2)(3)(4)
400 Mils
3 Processor HS bypass capacitor count per vdds_ddrx rail See Section 7.4 and
(11)
Devices
4 Processor HS bypass capacitor total capacitance per vdds_ddrx rail See Section 7.4 and
(11)
μF
5 Number of connection vias for each device power/ground ball
(5)
Vias
6 Trace length from device power/ground ball to connection via
(2)
35 70 Mils
7 Distance, HS bypass capacitor to DDR device being bypassed
(6)
150 Mils
8 DDR3 device HS bypass capacitor count
(7)
12 Devices
9 DDR3 device HS bypass capacitor total capacitance
(7)
0.85 μF
10 Number of connection vias for each HS capacitor
(8)(9)
2 Vias
11 Trace length from bypass capacitor connect to connection via
(2)(9)
35 100 Mils
12 Number of connection vias for each DDR3 device power/ground ball
(10)
1 Vias
13 Trace length from DDR3 device power/ground ball to connection via
(2)(8)
35 60 Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
