Copyright © 2016–2017, Texas Instruments IncorporatedTerminal Configuration and Functions
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36
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
B21 mcasp2_axr3 mcasp2_axr3 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp3_axr3 1 IO 0
vin1a_d4 7 I 0
pr2_mii0_rxlink 11 I 0
pr2_pru0_gpi17 12 I
pr2_pru0_gpo17 13 O
gpio6_9 14 IO
Driver off 15 I
B20 mcasp2_axr4 mcasp2_axr4 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp8_axr0 1 IO 0
gpio1_4 14 IO
Driver off 15 I
C19 mcasp2_axr5 mcasp2_axr5 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp8_axr1 1 IO 0
gpio6_7 14 IO
Driver off 15 I
D20 mcasp2_axr6 mcasp2_axr6 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp8_aclkx 1 IO 0
mcasp8_aclkr 2 IO
gpio2_29 14 IO
Driver off 15 I
C20 mcasp2_axr7 mcasp2_axr7 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp8_fsx 1 IO 0
mcasp8_fsr 2 IO
gpio1_5 14 IO
Driver off 15 I
B22 mcasp3_axr0 mcasp3_axr0 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp2_axr14 2 IO 0
uart7_ctsn 3 I 1
uart5_rxd 4 I 1
vin1a_d1 7 I 0
pr2_mii1_rxer 11 I 0
pr2_pru0_gpi14 12 I
pr2_pru0_gpo14 13 O
Driver off 15 I