DDR_CLK
1
SPRS906_PCB_DDR3_01
354
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Applications, Implementation, and Layout Copyright © 2016–2017, Texas Instruments Incorporated
• Minimize ISI by keeping impedances matched.
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
• Use proper low-pass filtering on the Vref pins.
• Keep the stub length as short as possible.
• Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
• Maintain a common ground reference for all bypass and decoupling capacitors.
• Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
7.2.2 DDR3 Board Design and Layout Guidelines
7.2.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 7-2 and
Figure 7-1.
Table 7-2. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO. PARAMETER MIN MAX UNIT
1 t
c(DDR_CLK)
Cycle time, DDR_CLK 1.5 2.5
(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
Figure 7-1. DDR3 Memory Controller Clock Timing
7.2.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF.
7.2.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting,
Table 7-3 summarizes the supported device configurations.
Table 7-3. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS) MIRRORED? DDR3 EMIF WIDTH (BITS)
1 16 N 16
2 8 Y
(1)
16
2 16 N 32
2 16 Y
(1)
32
3 16 N
(3)
32
4 8 N 32
4 8 Y
(2)
32
5 8 N
(3)
32
