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AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Product Folder Links: AM5706 AM5708
Detailed DescriptionCopyright © 2016–2017, Texas Instruments Incorporated
• Power and clock management
– Debugger can get the status of the power domain associated to each TAP.
– Debugger may prevent the application software switching off the power domain.
– Application power management behavior can be preserved during debug across power transitions.
– For more information, see Power and Clock Management section of the Device TRM.
• Reset management
– Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
– For more information, see Reset Management section of the Device TRM.
• Cross-triggering
– Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to
another:
• Subsystem A can be programmed to generate a debug event, which can then be exported as a
global trigger across the device.
• Subsystem B can be programmed to be sensitive to the trigger line input and to generate an
action on trigger detection.
– Two global trigger lines are implemented
– Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the
debug subsystem
– Various ARM® CoreSight™ cross-trigger modules implemented to provide support for CoreSight
triggers distribution
• CoreSight Cross-Trigger Interface (CS_CTI) modules
• CoreSight Cross-Trigger Matrix (CS_CTM) modules
– For more information about cross-triggering, see Cross-Triggering section of the Device TRM.
• Suspend
– Provides a way to stop a closely coupled hardware process running on a peripheral module when
the host processor enters debug state
– For more information about suspend, see Suspend section of the Device TRM.
• MPU watchpoint
– Embedded in MPU subsystem
– Provides visibility on MPU to EMIF direct paths
– For more information, see MPU Memory Adaptor (MPU_MA) Watchpoint section of the Device
TRM.
• Processor trace
– Cortex-A15 (MPU) and C66x (DSP) processor trace is supported
– Program trace only for MPU (no data trace)
– MPU trace supported by a CoreSight Program Trace Macrocell (CS_PTM) module
– Three exclusive trace sinks:
• CoreSight Trace Port Interface Unit (CS_TPIU) – trace export to an external trace receiver
• CTools Trace Buffer Router (CT_TBR) in system bridge mode – trace export through USB
• CT_TBR in buffer mode – trace history store into on-chip trace buffer
– For more information, see Processor Trace section of the Device TRM.
