350
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Pulse-
Width Modulation Subsystem of the device TRM.
6.11 On-chip Debug
Debugging a system that contains an embedded processor involves an environment that connects high-
level debugging software running on a host computer to a low-level debug interface supported by the
target device. Between these levels, a debug and trace controller (DTC) facilitates communication
between the host debugger and the debug support logic on the target chip.
The DTC is a combination of hardware and software that connects the host debugger to the target system.
The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the
debugger user to JTAG
®
commands and scans that execute the core hardware.
The debug software and hardware components let the user control multiple central processing unit (CPU)
cores embedded in the device in a global or local manner. This environment provides:
• Synchronized global starting and stopping of multiple processors
• Starting and stopping of an individual processor
• Each processor can generate triggers that can be used to alter the execution flow of other processors
System topics include but are not limited to:
• System clocking and power-down issues
• Interconnection of multiple devices
• Trigger channels
For more information, see chapter On-chip Debug of the device TRM.
The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It
provides the following features:
• External debug interfaces:
– Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)
• Used for debugger connection
• Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7
adapter module
• Controls ICEPick™ (generic test access port [TAP] for dynamic TAP insertion) to allow the
debugger to access several debug resources through its secondary (output) JTAG ports (for
more information, see ICEPick Secondary TAPs section of the Device TRM).
– Debug (trace) port
• Can be used to export processor or system trace off-chip (to an external trace receiver)
• Can be used for cross-triggering with an external device
• Configured through debug resources manager (DRM) module instantiated in the debug
subsystem
• For more information about debug (trace) port, see Debug (Trace) Port and Concurrent Debug
Modes sections of the Device TRM.
• JTAG based processor debug on:
– Cortex-A15 in MPU
– C66x in DSP1
– Cortex-M4 (x2) in IPU1, IPU2
– ARM968 (x2) in IVA
• Dynamic TAP insertion
– Controlled by ICEPick
– For more information, see , Dynamic TAP Insertion.
