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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
6.10.14 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks.
Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus,
the general-purpose interface supports up to 256 (8 × 32) pins. Since some of the pins are reserved in this
Device, general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations.
• Wake-up request generation in idle mode upon the detection of external events
For more information, see section General-Purpose Interface (GPIO) of the device TRM.
6.10.15 ePWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
Each ePWM module supports the following features:
• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
– Two independent PWM outputs with single-edge operation
– Two independent PWM outputs with dual-edge symmetric operation
– One independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software.
• Programmable phase-control support for lag or lead operation relative to other ePWM modules.
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
• Dead-band generation with independent rising and falling edge delay control.
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault
conditions.
• A trip condition can force either high, low, or high-impedance state logic levels at PWM
outputs.
• Programmable event prescaling minimizes CPU overhead on interrupts.
• PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
For more information, see section Enhanced PWM (ePWM) Module in chapter Pulse-Width Modulation
Subsystem of the device TRM.
6.10.16 eCAP
Uses for eCAP include:
• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
