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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
341
AM5706, AM5708
www.ti.com
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed DescriptionCopyright © 2016–2017, Texas Instruments Incorporated
McASP8 supporting 2 channels with independent TX/RX clock/sync domain
For more information, see section Multichannel Audio Serial Port (McASP) in chapter Serial
Communication Interfaces of the device TRM.
6.10.9 USB
SuperSpeed USB DRD Subsystem has three instances in the device providing the following functions:
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY
SuperSpeed USB DRD Subsystem has the following features:
Dual-role-device (DRD) capability:
Supports USB Peripheral (or Device) mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps),
and FS (12 Mbps)
Supports USB Host mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps), FS (12 Mbps), and
LS (1.5 Mbps)
USB static peripheral operation
USB static host operation
Flexible stream allocation
Stream priority
External Buffer Control
Each instance contains single xHCI controller with the following features:
Internal DMA controller
Descriptor caching and data prefetching
Interrupt moderation and blocking
Power management USB3.0 states for U0, U1, U2, and U3
Dynamic FIFO memory allocation for all endpoints
Supports all modes of transfers (control, bulk, interrupt, and isochronous)
Supports high bandwidth ISO mode
Connects to an external charge pump for VBUS 5 V generation
USB-HS PHY (USB2PHY1 and USB2PHY2 for USB1 and USB2, respectively): contain the USB
functions, drivers, receivers, and pads for correct D+/D– signalling
For more information, see section SuperSpeed USB DRD (USB) in chapter Serial Communication
Interfaces of the device TRM.
6.10.10 PCIe
The Peripheral Component Interconnect Express (PCIe) module is a multi-lane I/O interconnect that
provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane,
per direction, for serial links on backplanes and printed wiring boards. It is a 3-rd Generation I/O
Interconnect technology succeeding PCI and ISA bus that is designed to be used as a general-purpose
serial I/O interconnect. It is also used as a bridge to other interconnects like USB2/3.0, GbE MAC, and so
forth.
The PCI Express standard predecessor - PCI, is a parallel bus architecture that is increasingly difficult to
scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe
architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the
necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It
is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its
practical performance limits while simplifying the interface design.
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