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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
337
AM5706, AM5708
www.ti.com
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed DescriptionCopyright © 2016–2017, Texas Instruments Incorporated
The watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt
to the device system modules following an overflow condition. The WD_TIMER2 timer serves resets to the
PRCM module (its interrupt outputs are unused).
WD_TIMER2 is located in the PD_WKUPAON power domain, and can run when the device is in lowest
power state (all power domains are off except always-on (AON) and WKUP).
The watchdog timer can be accessed, loaded, and cleared by registers through the L4_WKUP interface.
The watchdog timer has the 32-kHz clock for its timer clock input. WD_TIMER2 directly generates a warm
reset condition on overflow.
WD_TIMER2 connects to a single target agent port on the L4_WKUP interconnect.
The main features of the watchdog timer controllers are:
L4 slave interface support:
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
11-bit address bus width
Burst mode not supported
Write nonposted mode supported
Free-running 32-bit upward counter
Programmable divider clock source (2
n
where n = [0:7])
On-the-fly read/write register (while counting)
Subset programming model of the GP timer
The watchdog timer is reset either on power on or after a warm reset before it starts counting.
Reset or interrupt actions when a timer overflow condition occurs
The watchdog timer generates a reset or an interrupt in its hardware integration.
For more information, see section Timers of the device TRM.
6.10.4 I2C
The device contains five multimaster high-speed (HS) inter-integrated circuit (I
2
C) controllers (I2Ci
modules, where i = 1, 2, 3, 4, 5) each of which provides an interface between a local host (LH), such as a
digital signal processor (DSP), and any I
2
C-bus-compatible device that connects through the I
2
C serial
bus. External components attached to the I
2
C bus can serially transmit and receive up to 8 bits of data to
and from the LH device through the 2-wire I
2
C interface.
Each multimaster HS I
2
C controller can be configured to act like a slave or master I
2
C-compatible device.
I
2
C1 and I
2
C2 controllers have dedicated I
2
C compliant open drain buffers, and support Fast mode (up to
400Kbps).
I
2
C3, I
2
C4 and I
2
C5 controllers are multiplexed with standard LVCMOS IO and connected to emulate open
drain. I
2
C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high
when transmitting logic 1. These controllers support HS mode (up to 3.4Mbps).
For more information, see section Multimaster High-Speed I2C Controller (I2C) in chapter Serial
Communication Interfaces of the device TRM.
6.10.5 UART
The UART is a simple L4 slave peripheral that utilizes the DMA_SYSTEM or EDMA for data transfer or
IRQ polling via CPU. There are 10 UART modules in the device. Only one UART supports IrDA features.
Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
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