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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
Each timer (except TIMER12) can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz
clock. The selection of clock source is made at the power, reset, and clock management (PRCM) module
level. TIMER12 can be clocked only from the internal oscillator (on-die oscillator)
The following are the main features of the GP timer controllers:
• Level 4 (L4) slave interface support:
– 32-bit data bus width
– 32-/16-bit access supported
– 8-bit access not supported
– 10-bit address bus width
– Burst mode not supported
– Write nonposted transaction mode supported
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Compare and capture modes
• Autoreload mode
• Start/stop mode
• Programmable divider clock source (2
n
, where n = [0:8])
• Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
• Dedicated GP output signal for using the TIMERi_GPO_CFG signal
• On-the-fly read/write register (while counting)
• 1-ms tick with 32.768-Hz functional clock generated (only TIMER1, TIMER2, and TIMER10)
For more information, see section Timers of the device TRM.
6.10.3.2 32-kHz Synchronized Timer (COUNTER_32K)
The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-
kHz system clock.
The main features of the 32-kHz synchronized timer controller are:
• L4 slave interface (OCP) support:
– 32-bit data bus width
– 32-/16-bit access supported
– 8-bit access not supported
– 16-bit address bus width
– Burst mode not supported
– Write nonposted transaction mode not supported
• Only read operations are supported on the module registers; no write operation is supported (no
error/no action on write).
• Free-running 32-bit upward counter
• Start and keep counting after power-on reset
• Automatic roll over to 0; highest value reached: 0xFFFF FFFF
• On-the-fly read (while counting)
For more information, see section Timers of the device TRM.
6.10.3.3 Watchdog Timer
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2.