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AM5706BCBDDEA

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型号: AM5706BCBDDEA
PDF文件:
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
335
AM5706, AM5708
www.ti.com
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed DescriptionCopyright © 2016–2017, Texas Instruments Incorporated
Format conversion and scaling
Programmable color space conversion
YUV422 to YUV444 conversion
YUV444 to YUV422 conversion
YUV422 to YUV420 conversion
YUV444 Source: YUV444 to YUV444, YUV444 to RGB888, YUV444 to YUV422, YUV444 to
YUV420
RGB888 Source: RGB888 to RGB888, RGB888 to YUV444, RGB888 to YUV422, RGB888 to
YUV420
YUV422 Source: YUV422 to YUV422, YUV422 to YUV420, YUV422 to YUV444, YUV422 to
RGB888
Supports RAW to RAW (no processing)
Scaling and format conversions do not work for multiplexed input
Supports up to 2047 pixels wide input - when scaling is engaged
Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without
scaling
Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling
The maximum supported input resolution is further limited by:
Pixel clock and feature-dependent constraints
For RGB24-bit format (RAW data), the maximum frame width is limited to 2730 pixels
For more information, see chapter Video Input Port of the device TRM
6.10.2 DSS
Display Port Interfaces (DPI) is available in DSS named DPI Video Output (VOUT).
VOUT interface consists of:
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
For more information, see section Display Subsystem (DSS) of the device TRM.
6.10.3 Timers
The device includes several types of timers used by the system software, including 16 general-purpose
(GP) timers, one watchdog timer, and a 32-kHz synchronized timer (COUNTER_32K).
6.10.3.1 General-Purpose Timers
The device has 16 GP timers: TIMER1 through TIMER16.
TIMER1(1ms tick): has its event capture pin tied to 32KHz clock and can be used to gauge the system
clock input and detects its frequency among 19.2, 20, or 27 MHz. It includes a specific functions to
generate accurate tick interrupts to the operating system and it belongs to the PD_WKUPAON domain
TIMER2 and TIMER10: (1ms tick timers): they include a specific functions to generate accurate tick
interrupts to the operating system, TIMER2 and TIMER10 belong to the PD_L4PER domain
TIMER3/4/9/11/13/14/15/16: they belongs to the PD_L4PER domain
TIMER12 belongs to the PD_WKUPAON power domain
TIMER5 trough TIMER8: belong to the PD_IPU module
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