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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
334
AM5706, AM5708
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which
has two video input ports, Port A and Port B, where Port A can be configured as a 24/16/8-bit port, and
Port B is a fixed 8-bit port.
Each video Port A can be operated as a port with clock independent input channels (with interleaved or
separated Y/C data input). Embedded sync and external sync modes are supported for all input
configurations.
Support for a single external asynchronous pixel clock, up to 165MHz per port.
Pixel Clock Input Domain Port A supports up to one 24-bit input data bus, including BT.1120 style
embedded sync for 16-bit and 24-bit data.
Embedded Sync data interface mode supports single or multiplexed sources
Discrete Sync data interface mode supports only single source input
24-bit data input plus discrete syncs can be configured to include:
8-bit YUV422 (Y and U/V time interleaved)
16-bit YUV422 (CbY and CrY time interleaved)
24-bit YUV444
16-bit RGB565
24-bit RGB888
12/16-bit RAW Capture
24-bit RAW capture
Discrete sync modes include:
VSYNC + HSYNC (FID determined by FID signal pin or HSYNC/VSYNC skew)
VSYNC + ACTVID + FID
VBLANK + ACTVID (ACTVID toggles in VBLANK) + FID
VBLANK + ACTVID (no ACTVID toggles in VBLANK) + FID
Multichannel parser (embedded syncs only)
Embedded syncs only
Pixel (2x or 4x) or Line multiplexed modes supported
Performs demultiplexing and basic error checking
Supports maximum of 9 channels in Line Mux (8 normal + 1 split line)
Ancillary data capture support
For 16-bit or 24-bit input, ancillary data may be extracted from any single channel
For 8-bit time interleaved input, ancillary data can be chosen from the Luma channel, the Chroma
channel, or both channels
Horizontal blanking interval data capture only supported when using discrete syncs (VSYNC +
HSYNC or VSYNC + HBLANK)
Ancillary data extraction supported on multichannel capture as well as single source streams
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