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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
333
AM5706, AM5708
www.ti.com
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed DescriptionCopyright © 2016–2017, Texas Instruments Incorporated
Flexible transfer definition
Increment or constant addressing modes
Linking mechanism allows automatic PaRAM set update
Chaining allows multiple transfers to execute with one event
64 DMA channels
Channels triggered by either:
Event synchronization
Manual synchronization (CPU write to event set register)
Chain synchronization (completion of one transfer triggers another transfer)
Support for programmable DMA Channel to PaRAM mapping
8 Quick DMA (QDMA) channels
QDMA channels are triggered automatically upon writing to PaRAM set entry
Support for programmable QDMA channel to PaRAM mapping
512 PaRAM sets
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
2 transfer controllers/event queues
16 event entries per event queue
Interrupt generation based on:
Transfer completion
Error conditions
Debug visibility
Queue water marking/threshold
Error and status recording to facilitate debug
Memory protection support
Proxied memory protection for TR submission
Active memory protection for accesses to PaRAM and registers
Each EDMATC has the following features:
Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC
manages the 3rd dimension)
Up to 4 in-flight transfer requests (TR)
Programmable priority levels
Support for increment or constant addressing mode transfers
Interrupt and error support
Supports only little-endian operation in this device
Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR
For more information chapter EDMA Controller of the device TRM.
6.10 Peripherals
6.10.1 VIP
The VIP module provides video capture functions for the device. VIP incorporates a multi-channel raw
video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)
engine to store incoming video in various formats. The device uses a single instantiation of the VIP
module giving the ability of capturing up to two video streams.
A VIP module includes the following main features:
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