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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
制造商LOGO: TI1[TI store] LOGO
制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
324
AM5706, AM5708
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
TMS320C66x DSP CorePac memory components:
A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:
When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache
line
The DSP CorePac L1P memory controller provides bandwidth management, memory
protection, and power-down functions
The L1P is capable of cache block and global coherence operations
The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM
The L1P memory can be fully configured as a cache or SRAM
Page size for L1P memory is 2KB
A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache
line
The DSP CorePac L1D memory controller provides bandwidth management, memory
protection, and power-down functions
The L1D memory can be fully configured as a cache or SRAM
No support for error correction or detection
Page size for L1D memory is 2KB
A 288-KiB (program and data) L2 memory, only part of which is cacheable:
When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte
cache line
Only 256 KiB of L2 memory can be configured as cache or SRAM
32 KiB of the L2 memory is always mapped as SRAM
The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including
necessary SRAM
The L2 memory controller supports hardware prefetching and also provides bandwidth
management, memory protection, and power-down functions.
Page size for L2 memory is 16KB
The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP
subsystem and device. It has :
a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA,
DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.
a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP
subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the
DSP subsystem is the slave in a transaction.
The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which
are a result of CPU instruction fetches, load/store commands, cache operations) to device resources
via the C66x DSP CorePac 128-bit master DMA (MDMA) port:
Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on
the MDMA port
Prefetch, multi-in-flight requests
A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to
the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt
controller supports up to 128 system events of which 64 interrupts are external to DSP subsystem,
collected from the DSP1 dedicated outputs of the device Interrupt Crossbar.
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