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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
• Interfaces:
– 128-bit interface to EMIF1
– 64-bit master port to the L3_MAIN interconnect
– 32-bit slave port from the L4_CFG_EMU interconnect (debug subsystem) for configuration of the
MPU subsystem debug modules
– 32-bit slave port from the L4_CFG interconnect for memory adapter firewall (MPU_MA_NTTP_FW)
configuration
– 32-bit ATB output for transmitting debug and trace data
– 160 peripheral interrupt inputs
For more information, see section ARM Cortex-A15 Subsystem in chapter Processors and Accelerators of
the device TRM.
6.4 DSP Subsystem
The device includes a single instance (DSP1) of a digital signal processor (DSP) subsystem, based on the
TI's standard TMS320C66x™ DSP CorePac core.
The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating
point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible
with the C64x+/C674x DSPs.
For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set
Reference Guide, (SPRUGH7).
The DSP subsystem integrated in the device includes the following components:
• A TMS320C66x™ CorePac DSP core that encompasses:
– L1 program-dedicated (L1P) cacheable memory
– L1 data-dedicated (L1D) cacheable memory
– L2 (program and data) cacheable memory
– Extended Memory Controller (XMC)
– External Memory Controller (EMC)
– DSP CorePac located interrupt controller (INTC)
– DSP CorePac located power-down controller (PDC)
• Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and
peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The
external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from
the DSP1 dedicated outputs of the device DMA Events Crossbar for the subsystem.
• A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the
subsystem or the remainder of the device via the device L3_MAIN interconnect.
• Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the
device L3_MAIN interconnect address space
• Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation,
and connection to the device power, reset, and clock management (PRCM) module
The TMS320C66x Instruction Set Architecture ( ISA™) is the latest for the C6000 family. As with its
predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional
units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total
of 64 general-purpose 32-bit registers.
Some features of the DSP C6000 family devices are:
• Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:
– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
– Allows designers to develop highly effective RISC-like code for fast development time
