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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated
• ARM
®
Cortex-A15 MP Core™ (MPU_CLUSTER)
– One Cortex-A15 MPU core (revision r2p2) which has the following features:
• Superscalar, dynamic multi-issue technology
– Out-of-order (OoO) instruction dispatch and completion
– Dynamic branch prediction with branch target buffer (BTB), global history buffer (GHB), and
48-entry return stack
– Continuous fetch and decoding of three instructions per clock cycle
– Dispatch of up to four instructions and completion of eight instructions per clock cycle
– Provides optimal performance from binaries compiled for previous ARM processors
– Five execution units handle simple instructions, branch instructions, Neon™ and floating
point instructions, multiply instructions, and load and store instructions.
– Simple instructions take two cycles from dispatch, while complex instructions take up to 11
cycles.
– Can issue two simple instructions in a cycle
– Can issue a load and a store instruction in the same cycle
• Integrated Neon processing engine to include the ARM Neon Advanced SIMD (single
instruction, multiple data) support for accelerated media and signal processing computation
• Includes VFPv4-compatible hardware to support single- and double-precision add, subtract,
divide, multiply and accumulate, and square root operations
• Extensive support to accelerate virtualization using a hypervisor
• 32-KiB L1 instruction (L1I) and 32-KiB L1 data (L1D) cache:
– 64-byte line size
– 2-way set associative
• Memory management unit (MMU):
– Two-level translation lookaside buffer (TLB) organization
– First level is an 32-entry, fully associative micro-TLB implemented for each of instruction
fetch, load, and store.
– Second level is a unified, 4-way associative, 512-entry main TLB
– Supports hardware TLB table-walk for backward-compatible and new 64-bit entry page table
formats
– New page table format can produce 40-bit physical addresses
– Two-stage translation where first stage is HLOS-controlled and the second level may be
controlled by a hypervisor. Second stage always uses the new page table format
– Integrated L2 cache (MPU_L2CACHE) and snoop control unit (SCU):
• 1-MiB of unified (instructions and data) cache organized as 16 ways of 1024 sets of 64-byte
lines
• Redundant L1 data (cache) tags to perform snoop filtering (L1 instruction cache tags are not
duplicated)
• Operates at Cortex-A15 MPU core clock rate
• Integrated L2 cache controller (MPU_L2CACHE_CTRL):
– Sixteen 64-byte line buffers that handle evictions, line fills and snoop transfers
– One 128-bit AMBA4 Coherent Bus (AXI4-ACE) port
– Auto-prefetch buffer for up to 16 streams and detecting forward and backward strides
– Generalized interrupt controller (GIC, also referred to as MPU_INTC): An interrupt controller
supplied by ARM. The single GIC in the MPU_CLUSTER routes interrupts to the MPU core. The
GIC supports:
• Number of shared peripheral interrupts (SPI): 160
• Number of software generated interrupts (SGI): 16
• Number of CPU interfaces: 1
