TRACECLK
TRACECTL
TRACEDATA[X:0]
TPIU4 TPIU4
TPIU2
TPIU1
TPIU3
TPIU5 TPIU5
SPRS906_TIMING_TIMER_01
315
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
5.9.7.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 5-196.
5.9.7.2.1 TPIU PLL DDR Mode
Table 5-195 and Figure 5-127 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 5-195. Switching Characteristics for TPIU
NO. PARAMETER DESCRIPTION MIN MAX UNIT
TPIU1 t
c(clk)
Cycle time, TRACECLK period 5.56 ns
TPIU4 t
d(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL transition -1.61 1.98 ns
TPIU5 t
d(clk-dataV)
Skew time, TRACECLK transition to TRACEDATA[17:0] -1.61 1.98 ns
Figure 5-127. TPIU—PLL DDR Transmit Mode
(1)
(1) In d[X:0], X is equal to 15 or 17.
In Table 5-196 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
Table 5-196. TPIU IOSETs
SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
emu19 E10 5
emu18 B10 5
emu17 A10 5
emu16 F10 5
emu15 A11 5
emu14 A8 5
emu13 A9 5
emu12 A7 5
emu11 B9 5
emu10 C8 5
emu9 B8 5
emu8 E8 5
emu7 C7 5
emu6 B7 5