308
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-183. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode (continued)
BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
AA2 mmc3_dat1 2000 1700 CFG_MMC3_DAT1_OUT pr2_pru0_gpo5
AA3 mmc3_dat2 2050 2200 CFG_MMC3_DAT2_OUT pr2_pru0_gpo6
W2 mmc3_dat3 2000 2000 CFG_MMC3_DAT3_OUT pr2_pru0_gpo7
Y3 mmc3_dat4 2150 2600 CFG_MMC3_DAT4_OUT pr2_pru0_gpo8
AA1 mmc3_dat5 2400 2600 CFG_MMC3_DAT5_OUT pr2_pru0_gpo9
AA4 mmc3_dat6 2200 2300 CFG_MMC3_DAT6_OUT pr2_pru0_gpo10
AB1 mmc3_dat7 1800 2400 CFG_MMC3_DAT7_OUT pr2_pru0_gpo11
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET1
Direct Input mode. See Table 5-29 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 5-184 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input
mode for a definition of the Manual modes.
Table 5-184 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-184. Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode
BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
P5 RMII_MHZ_50_CL
K
1400 1200 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
L6 mdio_d 1300 1600 CFG_MDIO_D_IN pr2_pru1_gpi1
L5 mdio_mclk 1400 800 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
N2 rgmii0_rxc 1400 500 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
P2 rgmii0_rxctl 1400 1800 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
N4 rgmii0_rxd0 1400 1300 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
N3 rgmii0_rxd1 1400 1650 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
P1 rgmii0_rxd2 1400 1400 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
N1 rgmii0_rxd3 1400 1650 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
T4 rgmii0_txc 1400 900 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
T5 rgmii0_txctl 1400 1300 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
R1 rgmii0_txd0 1400 900 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
R2 rgmii0_txd1 1300 1400 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
P3 rgmii0_txd2 1300 1100 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
P4 rgmii0_txd3 1300 1300 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
N5 uart3_rxd 1300 1000 CFG_UART3_RXD_IN pr2_pru1_gpi3
N6 uart3_txd 1300 800 CFG_UART3_TXD_IN pr2_pru1_gpi4
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU1 IOSET2
Direct Input mode. See Table 5-29 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 5-185 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input
mode for a definition of the Manual modes.
Table 5-185 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.