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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-182. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode
BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
Y5 gpio6_10 1000 3300 CFG_GPIO6_10_IN pr2_pru0_gpi0
Y6 gpio6_11 1000 3400 CFG_GPIO6_11_IN pr2_pru0_gpi1
F16 mcasp1_axr15 0 1300 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20
E19 mcasp2_aclkx 0 800 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18
A21 mcasp2_axr2 0 1900 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
B21 mcasp2_axr3 0 1400 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17
D19 mcasp2_fsx 0 1400 CFG_MCASP2_FSX_IN pr2_pru0_gpi19
B22 mcasp3_axr0 0 1400 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
B23 mcasp3_axr1 0 1000 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
A23 mcasp3_fsx 0 1300 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
Y2 mmc3_clk 1000 3700 CFG_MMC3_CLK_IN pr2_pru0_gpi2
Y1 mmc3_cmd 1000 3500 CFG_MMC3_CMD_IN pr2_pru0_gpi3
Y4 mmc3_dat0 1000 3500 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AA2 mmc3_dat1 1000 4000 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AA3 mmc3_dat2 1000 3300 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
W2 mmc3_dat3 1000 3900 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
Y3 mmc3_dat4 1000 3500 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AA1 mmc3_dat5 1000 3600 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AA4 mmc3_dat6 1000 3500 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB1 mmc3_dat7 1000 3100 CFG_MMC3_DAT7_IN pr2_pru0_gpi11
A22 mcasp3_aclkx 0 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2
Direct Output mode. See Table 5-29 Modes Summary for a list of IO timings requiring the use of Manual
IO Timings Modes. See Table 5-183 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct
Output mode for a definition of the Manual modes.
Table 5-183 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-183. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode
BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
Y5 gpio6_10 1800 1900 CFG_GPIO6_10_OUT pr2_pru0_gpo0
Y6 gpio6_11 2500 2100 CFG_GPIO6_11_OUT pr2_pru0_gpo1
F16 mcasp1_axr15 0 400 CFG_MCASP1_AXR15_OUT pr2_pru0_gpo20
E19 mcasp2_aclkx 0 400 CFG_MCASP2_ACLKX_OUT pr2_pru0_gpo18
A21 mcasp2_axr2 0 500 CFG_MCASP2_AXR2_OUT pr2_pru0_gpo16
B21 mcasp2_axr3 0 500 CFG_MCASP2_AXR3_OUT pr2_pru0_gpo17
D19 mcasp2_fsx 0 0 CFG_MCASP2_FSX_OUT pr2_pru0_gpo19
A22 mcasp3_aclkx 0 500 CFG_MCASP3_ACLKX_OUT pr2_pru0_gpo12
B22 mcasp3_axr0 0 0 CFG_MCASP3_AXR0_OUT pr2_pru0_gpo14
B23 mcasp3_axr1 0 200 CFG_MCASP3_AXR1_OUT pr2_pru0_gpo15
A23 mcasp3_fsx 0 300 CFG_MCASP3_FSX_OUT pr2_pru0_gpo13
Y2 mmc3_clk 2100 2200 CFG_MMC3_CLK_OUT pr2_pru0_gpo2
Y1 mmc3_cmd 2300 2300 CFG_MMC3_CMD_OUT pr2_pru0_gpo3
Y4 mmc3_dat0 2000 1600 CFG_MMC3_DAT0_OUT pr2_pru0_gpo4