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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-180. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode (continued)
BALL BALL NAME PR1_PRU1_DIR_OUT_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
C13 vin2a_d22 0 0 CFG_VIN2A_D22_OUT pr1_pru1_gpo19
D13 vin2a_d23 0 400 CFG_VIN2A_D23_OUT pr1_pru1_gpo20
A9 vin2a_d3 0 2200 CFG_VIN2A_D3_OUT pr1_pru1_gpo0
A8 vin2a_d4 540 2800 CFG_VIN2A_D4_OUT pr1_pru1_gpo1
A11 vin2a_d5 0 400 CFG_VIN2A_D5_OUT pr1_pru1_gpo2
F10 vin2a_d6 0 1500 CFG_VIN2A_D6_OUT pr1_pru1_gpo3
A10 vin2a_d7 0 2200 CFG_VIN2A_D7_OUT pr1_pru1_gpo4
B10 vin2a_d8 0 2600 CFG_VIN2A_D8_OUT pr1_pru1_gpo5
E10 vin2a_d9 0 2300 CFG_VIN2A_D9_OUT pr1_pru1_gpo6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Parallel
Capture Mode. See Table 5-29 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 5-181 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture
Mode for a definition of the Manual modes.
Table 5-181 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 5-181. Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture Mode
BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D10 vin2a_d10 1535 0 CFG_VIN2A_D10_IN pr1_pru1_gpi7
C10 vin2a_d11 1151 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
B11 vin2a_d12 1173 0 CFG_VIN2A_D12_IN pr1_pru1_gpi9
D11 vin2a_d13 970 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C11 vin2a_d14 1196 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
B12 vin2a_d15 1286 0 CFG_VIN2A_D15_IN pr1_pru1_gpi12
A12 vin2a_d16 1354 0 CFG_VIN2A_D16_IN pr1_pru1_gpi13
A13 vin2a_d17 1331 0 CFG_VIN2A_D17_IN pr1_pru1_gpi14
E11 vin2a_d18 2097 0 CFG_VIN2A_D18_IN pr1_pru1_gpi15
F11 vin2a_d19 0 453 CFG_VIN2A_D19_IN pr1_pru1_gpi16
A9 vin2a_d3 1566 0 CFG_VIN2A_D3_IN pr1_pru1_gpi0
A8 vin2a_d4 1012 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1
A11 vin2a_d5 1337 0 CFG_VIN2A_D5_IN pr1_pru1_gpi2
F10 vin2a_d6 1130 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3
A10 vin2a_d7 1202 0 CFG_VIN2A_D7_IN pr1_pru1_gpi4
B10 vin2a_d8 1395 0 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E10 vin2a_d9 1338 0 CFG_VIN2A_D9_IN pr1_pru1_gpi6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS2 PRU0 IOSET2
Direct Input mode. See Table 5-29 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 5-182 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input
mode for a definition of the Manual modes.
Table 5-182 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.